STEM Problem Detail

Problem Statement

Prompt

Provide me the solution of Question 6.6.

Solution Rendering...

## Problem 6.6 Solution

### Problem Statement

Complete the design of the ABEL and PLD-based ones counting circuit from Section 6.2.6. Use 22V10 or smaller PLDs, minimize the total number of PLDs required, and state the total delay in terms of worst-case PLD delays.

### Design Specifications

- **Input:** 16-bit data word $$D[15:0]$$
- **Output:** 5-bit binary count $$CNT[4:0]$$ (0 to 16)
- **PLD:** GAL22V10 or smaller
- **Goal:** Minimize number of PLDs and delay

### Design Approach: Tree-Structured Population Count

The optimal design uses a hierarchical approach:

1. Partition 16-bit input into four 4-bit groups
2. Count ones in each group (0-4) using 3-bit outputs
3. Sum the four 3-bit counts to produce final 5-bit result

### Optimized Implementation

#### Stage 1: Four 4-bit Ones Counters

Each 4-bit counter uses one GAL22V10:

- Inputs: $$D[3:0]$$ (4 bits)
- Outputs: $$C[2:0]$$ (3-bit count, 0-4)
- Equations (for one group):
\begin{align*}
C[0] &= D_0 \oplus D_1 \oplus D_2 \oplus D_3 \\
C[1] &= (D_0 \cdot D_1) \cdot \overline{D_2} \cdot \overline{D_3} + \overline{D_0} \cdot \overline{D_1} \cdot (D_2 \cdot D_3) \\
&\quad + (D_0 \oplus D_1) \cdot (D_2 \oplus D_3) \\
C[2] &= D_0 \cdot D_1 \cdot D_2 \cdot D_3
\end{align*}
- Product terms: $$C[0]$$: 8, $$C[1]$$: 12, $$C[2]$$: 1 (all ≤ 16)

#### Stage 2: Four-Input Adder

One GAL22V10 sums four 3-bit counts:

- Inputs: $$A[2:0]$$, $$B[2:0]$$, $$C[2:0]$$, $$D[2:0]$$ (12 bits total)
- Outputs: $$CNT[4:0]$$ (5-bit sum, 0-16)
- Implementation: Two-level addition
\[
CNT = A + B + C + D
\]
Optimized using carry-save addition:
\begin{align*}
S1 &= A + B \quad \text{(4-bit intermediate)} \\
S2 &= C + D \quad \text{(4-bit intermediate)} \\
CNT &= S1 + S2 \quad \text{(5-bit final)}
\end{align*}
- Product terms: Each output ≤ 16 terms

### PLD Allocation and Pin Assignment

| **PLD** | **Function** | **Inputs** | **Outputs** | **Product Terms** |
|---|---|---|---|---|
| GAL22V10-1 | Counter Group 0 | $$D[3:0]$$ | $$A[2:0]$$ | 21 |
| GAL22V10-2 | Counter Group 1 | $$D[7:4]$$ | $$B[2:0]$$ | 21 |
| GAL22V10-3 | Counter Group 2 | $$D[11:8]$$ | $$C[2:0]$$ | 21 |
| GAL22V10-4 | Counter Group 3 | $$D[15:12]$$ | $$D[2:0]$$ | 21 |
| GAL22V10-5 | Four-Input Adder | $$A,B,C,D[2:0]$$ | $$CNT[4:0]$$ | 62 |

### Product Term Optimization

#### 4-bit Counter Optimization

Original equations can be optimized:
\begin{align*}
C[0] &= D_0 \oplus D_1 \oplus D_2 \oplus D_3 \\
C[1] &= (D_0 \cdot D_1 \cdot \overline{D_2} \cdot \overline{D_3}) +
(\overline{D_0} \cdot \overline{D_1} \cdot D_2 \cdot D_3) + \\
&\quad (D_0 \cdot \overline{D_1} \cdot D_2 \cdot \overline{D_3}) +
(\overline{D_0} \cdot D_1 \cdot \overline{D_2} \cdot D_3) + \\
&\quad (D_0 \cdot \overline{D_1} \cdot \overline{D_2} \cdot D_3) +
(\overline{D_0} \cdot D_1 \cdot D_2 \cdot \overline{D_3})
\end{align*}
6 terms instead of 8 for $$C[1]$$.

#### Adder Optimization

The four-input adder uses carry-save technique:
\[
\begin{aligned}
&Sum1 = A + B \quad (4\text{-bit}) \\
&Sum2 = C + D \quad (4\text{-bit}) \\
&CNT = Sum1 + Sum2 \quad (5\text{-bit})
\end{aligned}
\]
Implemented in one PLD with shared intermediate terms.

### Delay Analysis

#### Critical Path

1. **Stage 1 (4-bit counter):** 1 PLD delay

- Input → Output through AND-OR array
- Typical $$t_{pd}$$: 15-25 ns
2. **Stage 2 (Four-input adder):** 1 PLD delay

- All inputs arrive simultaneously
- Single-level AND-OR logic
- Similar $$t_{pd}$$: 15-25 ns

#### Total Worst-Case Delay

\[
t_{total} = t_{PLD1} + t_{PLD2} = 2 \times t_{PLD}
\]
where $$t_{PLD} \approx 20$$ ns typical.

\[
\boxed{\text{Worst-case delay: 2 PLD delays}}
\]

### Alternative Designs Considered

#### Option A: Two 8-bit Counters (3 PLDs)

- Two PLDs for 8-bit counters
- One PLD for 2-input adder
- Problem: 8-bit counter needs >16 product terms per output
- **Not feasible** with GAL22V10

#### Option B: Direct 16-bit Counter (1 PLD)

- Single PLD implementation
- Problem: $$CNT[0]$$ = XOR of 16 inputs = $$2^{15}$$ terms
- **Not feasible** with GAL22V10

#### Option C: 2-bit Groups (8 PLDs)

- Eight 2-bit counters
- Tree of adders
- More PLDs, similar delay
- **Not optimal** for PLD count

### GAL16V8 Feasibility Check

Could we use smaller GAL16V8?

- 8 inputs maximum
- 4-bit counter needs 4 inputs → fits
- But 4-bit counter outputs need ≤8 product terms
- $$C[1]$$ needs 6 terms → fits
- $$C[0]$$ (XOR4) needs 8 terms → fits exactly
- **Result:** Possible with GAL16V8 but tight

GAL16V8 implementation would require:

- Four GAL16V8 for 4-bit counters
- One GAL22V10 for adder (needs more inputs)
- Total: 5 PLDs (same count)

### ABEL Implementation Example

```
module popcount_4bit
title '4-bit Ones Counter - GAL22V10'

" Inputs
D0, D1, D2, D3 pin 1, 2, 3, 4;

" Outputs
C0, C1, C2 pin 21, 22, 23 istype 'com';

equations

" LSB of count (parity)
C0 = D0 $ D1 $ D2 $ D3;

" Middle bit
C1 = (D0 & D1 & !D2 & !D3) # (!D0 & !D1 & D2 & D3) #
(D0 & !D1 & D2 & !D3) # (!D0 & D1 & !D2 & D3) #
(D0 & !D1 & !D2 & D3) # (!D0 & D1 & D2 & !D3);

" MSB of count
C2 = D0 & D1 & D2 & D3;

end
```

### Performance Characteristics

| **Parameter** | **Value** |
|---|---|
| Number of PLDs | 5 |
| Worst-case delay | 2 PLD delays |
| Typical delay | 40 ns (2 × 20 ns) |
| Maximum frequency | 25 MHz |
| Power consumption | ~450 mA (5 × 90 mA) |
| Board area | Moderate |
| Cost | Medium (5 PLDs) |

### Verification and Testing

Test vectors for verification:

1. All zeros: $$D=0$$ → $$CNT=00000$$
2. All ones: $$D=FFFF$$ → $$CNT=10000$$
3. Alternating: $$D=AAAA$$ → $$CNT=01000$$ (8 ones)
4. Single ones at each position
5. Random patterns

### Further Optimization Possibilities

#### 1. Pipelining

Add registers between stages:

- Stage 1 outputs registered
- Stage 2 uses registered inputs
- Increases throughput to 1 count per cycle
- Adds 1 cycle latency

#### 2. Resource Sharing

One PLD could implement two 4-bit counters if product terms allow:

- 8 inputs, 6 outputs
- $$C[0]$$ for two groups = XOR4 + XOR4
- Might exceed 16 terms for some outputs

#### 3. Custom Encoding

Use thermometer code or other encodings to reduce terms.

### Conclusion

The optimal design uses:

1. **Five GAL22V10 PLDs:**

- Four 4-bit ones counters
- One four-input adder
2. **Worst-case delay:** 2 PLD delays
3. **Product terms:** All within GAL22V10 limits
4. **Scalability:** Design extends easily to 32/64 bits

This design represents the optimal trade-off between PLD count and performance for a 16-bit ones counting circuit using standard PLDs.

5 GAL22V10s, 2 PLD delays. Optimal tree: four 4-bit counters + one four-input adder.

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Problem #81