STEM Problem Detail

Problem #77

Design and Technology Hard

Problem Statement

Prompt

Provide me the solution of Question 8.30.

Solution Rendering...

## Binary Rate Multiplier Design (7497-like Circuit)

## 8.30 Binary Rate Multiplier Design

Modify the circuit of Exercise 8.29 so that $$Z$$ produces $$N$$ transitions in each 16-tick interval. The resulting circuit is called a *binary rate multiplier*, and was once sold as a TTL MSI part, the 7497.

**Hint**: Gate the clock with the level output of the previous circuit.

## 1. Understanding the Requirement

In Exercise 8.29, we designed a circuit where output $$Z$$ is **asserted** (high) for exactly $$N$$ clock ticks during any 16-tick interval.

Now we need to modify it so that $$Z$$ produces $$N$$ **transitions** in each 16-tick interval. This means:

- Each transition is a rising edge or falling edge
- $$N$$ transitions means $$N/2$$ complete cycles if symmetric
- But $$N$$ can be odd, so we need a different approach

Actually, for a binary rate multiplier:

- Output $$Z$$ should have exactly $$N$$ pulses per 16 input clock cycles
- Each pulse is one clock period wide
- Pulse positions are evenly distributed

## 2. The 7497 Binary Rate Multiplier

The 7497 is a 6-bit binary rate multiplier that produces:
\[
f_{out} = \frac{N}{64} \cdot f_{in}
\]
where $$N$$ is a 6-bit binary input (0-63).

For our case with 4-bit input (16 input cycles), we want:
\[
f_{out} = \frac{N}{16} \cdot f_{in}
\]
This means $$N$$ output pulses per 16 input clock cycles.

## 3. Key Insight

From Exercise 8.29, we have a signal $$Z_{level}$$ that is high for $$N$$ clock cycles:
\[
Z_{level} = 1 \text{ when counter state } C < N
\]

If we gate the clock with this signal:
\[
Z_{pulse} = CLK \cdot Z_{level}
\]
Then $$Z_{pulse}$$ will have pulses only during the intervals when $$Z_{level}=1$$.

But this gives $$N$$ clock pulses, not necessarily $$N$$ transitions. Actually, each pulse has 2 transitions (rising and falling), so this gives $$2N$$ transitions.

We need something different: We want exactly $$N$$ output transitions.

## 4. Understanding Transitions vs. Pulses

Let's think carefully:

- A clock pulse has 2 transitions (rising and falling)
- If we output $$N$$ clock pulses, that's $$2N$$ transitions
- We want only $$N$$ transitions total
- For even $$N$$: $$N/2$$ complete pulses
- For odd $$N$$: $$(N-1)/2$$ complete pulses + 1 half pulse

Actually, looking at the 7497 datasheet: The output has exactly $$N$$ positive-going transitions per 64 input cycles. These are not necessarily symmetric pulses.

## 5. Correct Implementation

The 7497 works by using the input clock ANDed with various decoded outputs of a counter. The output is:
\[
Z = \sum_{i=0}^{5} (N_i \cdot CLK \cdot \text{decoded}_i)
\]
where $$\text{decoded}_i$$ is a signal that is high for specific clock cycles.

For a 4-bit version (16 cycles), we need:
\[
Z = \sum_{i=0}^{3} (N_i \cdot CLK \cdot \text{decoded}_i)
\]
where $$\text{decoded}_i$$ is high for $$2^i$$ specific, evenly spaced cycles.

## 6. Mathematical Basis

Consider a binary counter cycling through 0-15. Each bit toggles at a specific rate:

- LSB (Q0): toggles every clock cycle (16 transitions in 16 cycles)
- Q1: toggles every 2 cycles (8 transitions in 16 cycles)
- Q2: toggles every 4 cycles (4 transitions in 16 cycles)
- MSB (Q3): toggles every 8 cycles (2 transitions in 16 cycles)

If we take the clock ANDed with each bit's complement, we get pulses at specific positions:

- $$CLK \cdot \overline{Q_0}$$: pulses at odd-numbered cycles
- $$CLK \cdot \overline{Q_1}$$: pulses at cycles where Q1=0 (specific pattern)
- $$CLK \cdot \overline{Q_2}$$: pulses when Q2=0
- $$CLK \cdot \overline{Q_3}$$: pulses when Q3=0

These pulses are non-overlapping and evenly distributed.

## 7. How It Works

The output is:
\[
Z = N_3 \cdot (CLK \cdot \overline{Q_3}) + N_2 \cdot (CLK \cdot \overline{Q_2}) + N_1 \cdot (CLK \cdot \overline{Q_1}) + N_0 \cdot (CLK \cdot \overline{Q_0})
\]

Each term $$CLK \cdot \overline{Q_i}$$ produces pulses at specific positions:

- $$CLK \cdot \overline{Q_0}$$: Pulses at clock cycles 1, 3, 5, 7, 9, 11, 13, 15 (8 pulses)
- $$CLK \cdot \overline{Q_1}$$: Pulses at cycles 2-3, 6-7, 10-11, 14-15 (4 pulses)
- $$CLK \cdot \overline{Q_2}$$: Pulses at cycles 4-7, 12-15 (2 pulses)
- $$CLK \cdot \overline{Q_3}$$: Pulses at cycles 8-15 (1 pulse)

These pulse patterns are non-overlapping and their counts are powers of 2 (1, 2, 4, 8).

When weighted by binary weights $$N_i$$, we get exactly $$N$$ pulses per 16-clock cycle.

## 8. Pulse Distribution Table

| **Bit** | **Weight** | **Pulses per 16 cycles** | **Pulse positions (cycles)** |
|---|---|---|---|
| $$N_0$$ | 1 | 8 | 1, 3, 5, 7, 9, 11, 13, 15 |
| $$N_1$$ | 2 | 4 | 2-3, 6-7, 10-11, 14-15 |
| $$N_2$$ | 4 | 2 | 4-7, 12-15 |
| $$N_3$$ | 8 | 1 | 8-15 |

Total pulses: $$8N_0 + 4N_1 + 2N_2 + 1N_3 = N$$ (where $$N$$ is the binary number $$N_3N_2N_1N_0$$).

## 9. Example: N = 5 (0101)

- $$N_3=0$$, $$N_2=1$$, $$N_1=0$$, $$N_0=1$$
- Active terms: $$CLK \cdot \overline{Q_2}$$ (weight 4) and $$CLK \cdot \overline{Q_0}$$ (weight 1)
- Pulse positions:

## 10. Transition Counting

The output $$Z$$ is high whenever any of the weighted terms is high. We need to count rising edges in $$Z$$.

For $$N=5$$ (0101):

- Term 1 ($$CLK \cdot \overline{Q_0}$$): high at odd cycles
- Term 2 ($$CLK \cdot \overline{Q_2}$$): high at cycles 4-7 and 12-15
- Combined: high at cycles 1, 3, 4-7, 9, 11, 12-15

## 11. Correct Implementation (7497-style)

Looking at the actual 7497 datasheet, the output equation is:
\[
Z = \sum_{i=0}^{5} \left[ N_i \cdot (CLK \cap \text{decoded output } Y_i) \right]
\]
where $$Y_i$$ are specific decoded outputs from a 6-bit counter.

For our 4-bit version, we need decoded outputs that are high for specific sets of cycles. The standard approach uses:
\[
Y_0 = \overline{Q_0}
\]
\[
Y_1 = Q_0 \oplus Q_1
\]
\[
Y_2 = (Q_0 \cdot Q_1) \oplus Q_2
\]
\[
Y_3 = (Q_0 \cdot Q_1 \cdot Q_2) \oplus Q_3
\]

These $$Y_i$$ signals are high for exactly $$2^{3-i}$$ cycles, evenly distributed.

## 12. Output Equation

\[
Z = N_0 \cdot (CLK \cdot \overline{Q_0}) +
N_1 \cdot (CLK \cdot (Q_0 \oplus Q_1)) +
N_2 \cdot (CLK \cdot ((Q_0 Q_1) \oplus Q_2)) +
N_3 \cdot (CLK \cdot ((Q_0 Q_1 Q_2) \oplus Q_3))
\]

## 13. Verification

The $$Y_i$$ signals have the property:

- $$Y_0$$ is high for 8 cycles (even distribution)
- $$Y_1$$ is high for 4 cycles
- $$Y_2$$ is high for 2 cycles
- $$Y_3$$ is high for 1 cycle

When ANDed with CLK, each produces pulses at the rising edges during those cycles.

The total number of output transitions (rising edges) in 16 clock cycles is:
\[
\text{Transitions} = 8N_0 + 4N_1 + 2N_2 + 1N_3 = N
\]
where $$N$$ is the binary number $$N_3N_2N_1N_0$$.

## 14. Alternative Simplified Design

If we just need $$N$$ transitions (not necessarily evenly distributed), we can use the simpler approach from the hint:

From Exercise 8.29, we have $$Z_{level}$$ which is high when $$C < N$$. If we take:
\[
Z = CLK \cdot Z_{level}
\]
This gives pulses only when $$Z_{level}=1$$.

But this gives $$N$$ pulses, each with 2 transitions, so $$2N$$ transitions total.

To get exactly $$N$$ transitions, we need to output only the rising edges:
\[
Z = CLK \cdot Z_{level} \cdot \text{(some edge detection)}
\]

Actually, a simpler approach: Use $$Z_{level}$$ to gate the clock, but only output on alternate pulses. Or better: Output $$Z_{level}$$ XOR with a one-cycle delayed version of itself.

## 15. Edge Detection Method

Let $$Z_{level}$$ be the output from Exercise 8.29. Create:
\[
Z_{delayed} = Z_{level} \text{ delayed by one clock cycle}
\]
\[
Z = Z_{level} \oplus Z_{delayed}
\]

This produces a pulse (one clock period wide) at every transition of $$Z_{level}$$.

Since $$Z_{level}$$ has $$N$$ transitions per 16 cycles (it goes low-to-high at cycle 0, and high-to-low at cycle $$N$$), $$Z$$ will have exactly $$N$$ pulses per 16 cycles.

## 16. Complete Simplified Circuit

**Operation**:

1. $$Z_{level}$$ is high when counter state $$C < N$$
2. $$Z_{delayed}$$ is $$Z_{level}$$ delayed by one clock cycle
3. $$Z = Z_{level} \oplus Z_{delayed}$$ pulses for one clock cycle at each transition of $$Z_{level}$$
4. $$Z_{level}$$ has 2 transitions (rising at cycle 0, falling at cycle $$N$$)
5. Wait, that's only 2 transitions, not $$N$$...

Actually, $$Z_{level}$$ from Exercise 8.29 is high for $$N$$ consecutive cycles, so it has only 2 transitions. This doesn't give us $$N$$ transitions.

## 17. Correct Simple Design

The correct simple design based on the hint is actually:

From Exercise 8.29: $$Z_{level} = 1$$ when $$C < N$$.

If we output: $$Z = CLK$$ when $$Z_{level} = 1$$, then we get $$N$$ clock pulses, which is $$2N$$ transitions.

To get exactly $$N$$ transitions, we need to output only the rising edges of these pulses:
\[
Z = \text{rising edge of } (CLK \cdot Z_{level})
\]

This can be implemented with a one-shot or edge detector, but that's more complex.

## 18. Conclusion

The proper binary rate multiplier (7497-style) uses the first design with the XOR-based $$Y_i$$ signals. This produces exactly $$N$$ output transitions (rising edges) per 16 input clock cycles, with the transitions evenly distributed.

The key insight is that each bit of $$N$$ enables a set of clock pulses at specific, evenly spaced intervals, with the number of pulses weighted by binary powers (1, 2, 4, 8).

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